Embedded System News

Ceva’s Ceva-XC DSP core employs the company’s Ceva-X architecture to support 3.5 and 4G wireless designs. The new architecture accommodates one, two, or four vector-communication units alongside a single general computational unit to provide hardware support for as many as 64 simultaneous 16×16-bit MAC (multiply/accumulate) operations or 128 16×8-bit MAC operations when using all four vector units. Each vector unit is a 256-bit SIMD (single-instruction/multiple-data) engine using a three-way VLIW (very-long-instruction-word) architecture that supports as many as three parallel instructions, with each instruction operating on 256-bit registers.

Each engine can incorporate optional instruction sets to better balance between performance and cost to support transmitter functions, floating-point operations, and the CORDIC (coordinate-rotation-digital-computer) algorithm. Additional advanced hardware includes support for MIMO (multiple-input/multiple-output) detectors; channel estimation; and bit-chain processing for interleavers, scramblers, and FEC (forward-error-correction) encoders.

The execution units combine with the memory subsystem to enable a software implementation for LTE (long-term-evolution) Class 5 or WiMax (worldwide-interoperability-for-microwave-access) II designs that must support a downlink data rate of 300 Mbps with 4×4 MIMO. The memory subsystem employs AXI (advanced-extensible-interface) master and slave system buses that are configurable between 64- and 128-bit widths, and it includes an APB (advanced-peripheral-bus) 3 interface to support slow devices.

The memory subsystem supports caches; tightly coupled memories; and interfaces for emulation, profiling, and real-time trace modules. It supports optional EEC (extended error correction) for memory error detection and correction. The DMA (direct-memory-access) engine supports 2-D transfers that can operate in background data transfers and data-rate-matching modes.

The architecture supports a low-power interface protocol for managing power consumption through the power-scaling units in the system. The power-scaling units support five power modes, including automatically turning off the clock signal for unused units, supporting voltage and frequency scaling, and maintaining data memory.

The software-development tools for the Ceva-X include an optimizing C compiler, an IDE (integrated development environment), a debugger, simulators, and a profiler. Ceva offers optimized DSP and communication libraries. The host-level development tools run under Windows, Solaris, and Linux. The core is available for licensing now.

(1888PressRelease) March 11, 2009 – Toronto, Canada – The emulator is equipped with the latest drivers for both CCS3.3 and CCS2.x. This smart emulator prevents systems from crashing and becoming non-re-bootable in the event of power loss on the target board.

This portable, enhanced TI DSP emulator has a standard high-speed USB 2.0 interface, a data transfer rate of up to 480Mb/s, and remains compatible with USB1.1. It also has a standardized JTAG emulation interface which saves user’s computer resources. In addition, this emulator features plug-and-play set up for easy installation, it runs stable at high speeds, and GAO’s offering is competitively priced.

For more information about this GAO XDS510 USB 2.0 Enhanced TI DSP Emulator, please visit www.GAOEmbeded.com or contact

About GAO Embedded
GAO Embedded is a leading provider of embedded development tools that serve the needs of electronic professionals internationally.

For more information please visit http://www.GAOEmbedded.com.

Memory, cache and process node enhancements provide a cost-efficient performance boost for system savings and greater design flexibility

HOUSTON, March 11 /PRNewswire/ — Developers of data-intensive signal processing applications will benefit from the increased performance and value provided by the new TMS320C6457 digital signal processor (DSP), available at speeds of 1.2 GHz and 1 GHz from Texas Instruments Incorporated (TI) (NYSE: TXN). The C6457 delivers up to 30 percent more performance at one-third less the cost of current single core DSP processors from TI. This performance lift is due to several memory and cache enhancements, while the cost reduction is achieved through a smaller process node. These improvements provide system savings, greater efficiency and increased design flexibility for networking, military, imaging and industrial markets, in applications such as medical imaging, radar, industrial vision systems and test equipment (www.ti.com/c6457).

C6457 key features and benefits

* Based on TI’s industry-leading 1.2 GHz TMS320C64x+(TM) DSP core, the C6457 delivers 9,600 (16-bit) MMACS of peak performance for a cycle for cycle performance improvement of up to 30 percent.
* Performance improvements enabled by 2 MB of on-chip L2 memory (up to 1 MB cacheable), faster 32-bit DDR2 EMIF (667 MHz) and memory, cache and bus architecture enhancements. This gives customers the flexibility to add more channels to their designs as well as increased headroom for additional application features.
* High-speed interconnect available with Serial RapidIO (SRIO) and Gigabit Ethernet MAC serializer/deserializer (SERDES) interfaces for efficient inter-processor communications.
* On-chip acceleration for telecommunications applications with two Turbo-Decoder Coprocessors (TCP2) and one Viterbi Coprocessor (VCP2). This increases channel decoding operations to offload the DSP core, allowing more channels on a single processor for system cost savings.
* Backwards code compatible with other high performance C64x DSPs to enable legacy code reuse for a significantly shorter development cycle and increased design flexibility.

Pricing, availability, tools and support

TMX320C6457 samples are available today from TI and TI authorized distributors in a 23 x 23 mm BGA package. Pricing for the 1.2 GHz version is $146 USD and the 1 GHz version is $112 USD (both in 1K unit volume).

Developers can get started with the C6457 Evaluation Module (EVM). This easy-to-use development tool includes two on-board C6457 processors, high-speed DSP interconnect with Gigabit Ethernet MAC and Serial RapidIO SERDES interfaces, embedded JTAG emulation with an XDS560T trace pod header and a board-specific Code Composer Studio(TM) Integrated Development Environment. It also includes several TI analog power management devices and a clock driver to improve system performance. Order entry is open for the TMDXEVM6457 at $1995 USD (www.ti.com/c6457evm).

Find out more about the C6457 digital signal processor or TI’s high performance portfolio of products by visiting the links below:

* TMS320C6457 general information: www.ti.com/c6457
* TMS320C6457 product folder: www.ti.com/c6457pf
* TMS320C6457 EVM: www.ti.com/c6457evm
* DSP selection tool: www.ti.com/dsptool
* Learn more about TI’s high performance processors, including the C6457 and how to achieve faster performance with Serial RapidIO, at the TI Technology Day San Jose, April 1 – 2. Register now at http://www.ti.com/techdays2009.
* System block diagrams featuring the C6457: High-Speed Data Acquisition Front End and Ultrasound System
* Complementary Analog power solutions: www.ti.com/processorpower
* TI’s embedded processors: www.ti.com/processorspr
* TI E2E Community and support: http://community.ti.com/forums
* Follow TI on Twitter: www.twitter.com/txinstruments

Texas Instruments (NYSE: TXN) helps customers solve problems and develop new electronics that make the world smarter, healthier, safer, greener and more fun. A global semiconductor company, TI innovates through design, sales and manufacturing operations in more than 30 countries. For more information, go to www.ti.com.

Trademarks

TMS320C64x+ and Code Composer Studio are trademarks of Texas Instruments. All other trademarks and registered trademarks are the property of their respective owners.

SOURCE Texas Instruments Incorporated.